ESD impact on production yield and product quality is increasingly becoming more significant due to requirements for higher speeds and device scaling. In general, ESD protection devices work by providing a path through the integrated circuit (IC) that has high current shunting capabilities. High holding voltage (VH) enables latch-up safe operation of such devices. However, known high voltage (HV) gate-grounded N-channel metal oxide semiconductor (GGNMOS) clamps exhibit low VH, e.g., below drain voltage (VVDD). In addition, known solutions fail to provide designers with the ability to efficiently control/scale VH without comprising the device area.
A need therefore exists for methodology enabling formation of an ESD device that exhibits high VH and enables efficient control of Vt1 and VH without compromising the device area and the resulting device.